As the integration density of semiconductor devices continues to increase and the critical dimensions associated with such devices continue to decrease, there has been a corresponding increase in interest in identifying materials and processes for producing interest in low resistance materials to maintain or reduce signal delay. Silica and salicide (self-aligned silicide) materials and processes have been widely used to lower the sheet resistance and contact resistance for the gate conductor and source/drain regions of CMOS devices.
A number of metals, including tungsten, tantalum, zirconium, titanium, hafnium, platinum, palladium, vanadium, niobium, cobalt, nickel and various alloys of such metals have been used to form silicide layers on semiconductor devices. For gate lengths below about 100 nm, however, conventional salicide processes and materials tend to experience a variety of difficulties including opens, residues and layer non-uniformity, resulting at least in part from agglomeration within the silicide material layer.
These difficulties tend to be exacerbated by the high-temperature processing required to react most metal(s) with silicon to form the desired silicide layers. The high temperature anneals required also raise concerns regarding the impact of the silicide annealing process(es) on the thermal budget for the devices being manufactured. For example, when cobalt is used to form the silicide, the initial stoichiometry of the silicide may be generally represented as CoSi, but as the annealing process continues, particularly at higher temperatures, the silicide tends to incorporate an increasing amount of silicon and approaches a composition more closely represented as CoSi2 For devices having gate lengths below about 100 nm, however, the second high temperature silicidation used in conventional Co salicide processes tends to induce agglomeration within the silicide material layer, increasing the degree of non-uniformity within the layer and tending to degrade the performance of the resulting devices.
Nickel is an attractive metal for forming silicides because the annealing process required to form the desired silicide may be conducted at a relatively low temperature, e.g., below about 550 C. Due to the low silicidation temperature, NiSi exhibits a decreased tendency to agglomerate and form a silicide layer with a low sheet resistance that is generally independent of the device dimensions, increasing its utility for lowering the resistance of fine line structures.
One problem with the use of nickel in the silicides employed in CMOS devices arises from its relatively high diffusion coefficient. As a result nickel diffuses into the channel region located the gate conductor. This encroachment by the nickel into the body region degrades device performance.
Accordingly, it would be desirable to provide a CMOS device in which nickel employed in the silicide material is prevented from encroaching on the channel region by diffusion.